Vector Accelerator for RISC-V architecture - Diglab
Figure 1 from A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators | Semantic Scholar
GEMM based on the RISC-V Vector Extension (Part 1) | Luffca
SiFive VIU75 Accelerates Vector Math - AB Open
NSITEXE teams for RISC-V edge AI platform ...
SiFive's brand-new P550 is one of the world's fastest RISC-V CPUs | Ars Technica
SiFive reveals X280 core and AndeSight RISC-V IDE moves to v5.0
RISC-V processor with vector extension certified for ISO 26262 ASIL D ready
64-bit CPU with RISC-V Vector Extension
Vector Extension Proposal
RISC-V - Wikipedia
GEMM based on the RISC-V Vector Extension (Part 2) | Luffca
RISC-V Vector Extension in a Nutshell (Part 4): permute operations : r/asm
Enhancing RISC-V Vector Extensions to Accelerate... - SemiWiki
SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions - CNX Software
Tutorial: RISC-V Vector Extension Demystified - 2020 RISC-V Summit - YouTube
RISC-V Vector Extension
64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
What is the RISC-V ecosystem?
A “New Ara” for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
Extending the RISC-V architecture with domain specific accelerators - Embedded.com
Vector Extension 0.7 - YouTube
Expanding a RISC-V Processor with Vector Instructions for Accelerating Machine Learning - YouTube
Accelerator Processor - European Processor Initiative
Running Auto-Vectorized Program on RISC-V Vector RTL Simulator | Luffca
